1. Field of the Invention
The present invention relates to a semiconductor device such as insulated gate field effect transistors (MOSFETs) or MOS integrated circuits including MOSFETs, and more specifically, to a vertical MOSFET which has a trench structure with a U-shaped cross section.
2. Description of the Related Art
Recently, there has been developed vertical MOSFETs having a trench structure capable of more reducing the cell size.
FIG. 7 shows a cross section of a trench structure of a conventional N-channel vertical MOSFET.
In this figure, reference numeral 10 denotes an N.sup.+ -type semiconductor substrate, 11 an N-type epitaxial layer, 12 a P-type layer for providing a channel, 13 an N.sup.+ -type source region, and 14 a U-shaped trench extending from the surface of the source region 13 through a portion of the P-type layer 12 to reach the epitaxial layer 11, respectively.
Further, reference numeral 15 denotes a gate insulation film formed on the inner wall of the trench 14, and 16 denotes a polysilicon gate electrode formed on the gate insulation film 15 so as to fill the trench 14.
Since the vertical MOSFET has the gate electrode 16 provided in the trench 14, the cell size can be reduced, and the on-resistance can be also lowered.
The operating principle of the N-channel vertical MOSFET will now be explained.
The source region 13 is grounded, and a positive voltage is applied to the semiconductor substrate 10 (drain region) and the gate electrode 16. In this case, as the gate voltage is increased, a side surface region of the P-type layer 12, which is opposed to the gate electrode 16, is inverted to provide an inversion layer (channel region). Hence, electrons flow from the source region 13 to the drain region (epitaxial layer 11 and semiconductor substrate 10) located directly underneath the inversion layer.
However, when the vertical MOSFET is actually manufactured, it has disadvantages in its characteristics. That is, unwanted phenomena would occur such that the film thickness and film quality of the gate insulation film 15 at the upper corner of the trench 14 are different from those at another portion. As a result, the threshold voltage V.sub.th and the output characteristics (I.sub.ds, g.sub.m) at the upper corner may be different from that at another portions, resulting in unbalanced characteristics.
For preventing the disadvantage in the gate insulation film 15 at the side surface of the trench 14, it has been considered to smoothly round the upper corner of the gate insulation film 15, or improve the quality of the gate insulation film 15 formed in the inner wall of the trench 14.
In order to enhance the thermal stress of the gate insulation film, the bias stress, and the long life reliability, a multilayer (composite) gate film having an O (oxide)/N (nitride)/O (oxide) structure, which is composed of a thermal oxide film, a nitride film, and a CVD oxide film, has been used as a trench capacitor employed in 4MDRAMs (4M-bit dynamic semiconductor memory). It has been known that the dielectric breakdown electric field strength of the trench capacitor depends generally on both the radius of curvature (rounding amount) of the upper corner of the trench, and the equivalent silicon dioxide thickness of the composite gate film.
FIG. 8 shows the calculation results of the dependence of the dielectric breakdown electric field strength of the trench capacitor on the gate oxide film thickness in the case where the radius of curvature of the upper corner of the trench is 100 .ANG. (10 nm) and 400 .ANG. (40 nm). (The calculations were carried out with the assumption that an intrinsic breakdown electric field strength of the oxide film is given by 8 MV/cm.)
As for the trench capacitor in the 4MDRAM, a large capacity and a high dielectric breakdown electric field strength are required. Therefore, it is necessary that a thin gate film having a thickness of 15 nm or less have a dielectric breakdown electric field strength of 7 MV/cm or higher.
In fact, it is reported that the breakdown electric field strength of the trench capacitor of the 4MDRAM is 7 MV/cm or higher, which coincides with the results of the above calculation in the case where the radius of curvature a of the composite gate film of the upper corner of the trench is 15 nm, and the intrinsic breakdown electric field strength of the 0/N/0 composite gate film is 10 MV/cm.
As for the vertical MOSFET, when the guaranteed value of the gate breakdown voltage and the gate threshold voltage are given by 20 V and 1.0 V-2.0 V, respectively, as its specifications, it is required that the equivalent silicon dioxide thickness is limited to 50-65 nm, and the change in the gate threshold voltage does not occur.
It may be considered that the composite gate film having an O/N/O structure described above is employed as the gate insulation film formed on the inner wall of the trench 14.
However, since a MOSFET having the composite gate film has a problem such that the threshold voltage of the gate varies at an electric field of 6 MV/cm or more, the composite gate film is not employed as the gate insulation film of the inner wall of the trench 14 of the vertical MOSFET.
As described above, the change in the gate threshold voltage occurs at the electric field of 6 MV/cm or higher in the trench type MOSFET using the composite gate film. The followings show results to prove the fact described above by forming a capacitor having a flat gate structure as an evaluation sample.
FIG. 9 shows a cross section of the capacitor having the flat gate structure formed as the evaluation sample.
This figure illustrates an N-type semiconductor substrate 100, a plate electrode 101, and a composite gate film 103 having an O/N/O structure whose equivalent silicon dioxide thickness t.sub.ox is given by 50 nm.
FIG. 10 shows the leakage current of the gate film 102 when the DC bias voltage is applied between the plate electrode 101 of the capacitor having the flat gate structure shown in FIG. 9, and the semiconductor substrate 100. In this case, the leakage current value is given by the gate area per 0.1 cm.sup.2.
FIG. 11 shows a relationship between a DC bias application time and a variation in a flat band voltage V.sub.FB in the case where a voltage applied to capacitor of FIG. 10, is +30 V or `30 V (equivalent to the breakdown electric field strength of 6 MV/cm), and in the case where the applied voltage is +40 V or -40 V (equivalent to the breakdown electric field strength of 8 MV/cm).
It can be understood from FIGS. 10 and 11 that when
leakage current flowing through the gate film exceeds 1 .mu.A at the applied voltage of 40 V, carriers are trapped in the interface between films of the composite gate structure, resulting in a variation in flat-band voltage V.sub.FB due to the film interface electric field.
This means that when the gate structure is applied to the MOSFET and the electric field of 6 MV/cm or more is applied thereto, the variation in the threshold voltage of the gate of the MOSFET occurs.
At any rate, in the conventional vertical MOSFET, when the composite gate film having the 0/N/0 structure is adopted in order to improve the thermal stress, the bias stress, and the long life reliability of the gate insulation film, the variation in the threshold voltage of the gate would occur at an electric field of 6 MV/cm or more.